We have open PhD positions in the Integrated System Design Lab. Interested candidates, please email your CV mentioning your GATE score.
About
I am a faculty member in the Department of Electrical Engineering at IIT Ropar. I lead the Integrated System Design Lab (ISDL), focusing on analog integrated circuit design for computing (neuromorphic and quantum) and sensing applications. I am a senior IEEE member. Prior to joining academia, I worked at the GE Technology Centre (2010-12) and the R&D division of Siemens (2017-18). I am an avid reader.
Professional Highlights
Founded Integrated System Design Lab (ISDL) at IIT Ropar: Established a state-of-the-art research facility in 2018, enabling 5 research projects in CMOS analog/mixed-signal IC design, neuromorphic computing, and sensor interfacing circuits.
Led IIT Ropar’s First Tapeout: Successfully completed the institute’s first silicon tapeout, validating novel circuit designs.
Mentored 6 PhD Scholars: Supervised 6 PhD scholars to graduation, contributing to 12+ publications in analog and mixed-signal integrated circuit design.
Secured USD 0.4M in Grants: Obtained funding across 5 major projects from 2018–2025 for research in CMOS amplifiers, dynamic comparators, and cryo-CMOS circuits through projects like DST - National Quantum Mission, DoT - Telecom Technology Development, ANRF - Core Research Grant and MeitY - Chips to Start-up (C2S).
Published in Top Journals: Authored papers in IEEE TCAS-I, TCAS-II, Transactions on Electromagnetic Compatibility (TEMC) and Transactions on Electron Devices (TED), advancing analog, mixed-signal and neuromorphic IC design.
Shivdeep, S. Sharma, M. Sakare and D. M. Das, "Mitigating EMI Susceptibility in Three OpAmp INA With a High CMRR EMI Immune OTA," in IEEE Transactions on Electromagnetic Compatibility, doi: 10.1109/TEMC.2026.3677893.
N. Sharma, S. A. Thomas, V. Hande and D. M. Das, "A Modified Three Stage Dynamic Comparator Achieving Rail-to-Rail Input Common-Mode Range With <86 fJ · ns EDP," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 11, pp. 1540-1544, Nov. 2025, doi: 10.1109/TCSII.2025.3581335.
S. K. Vohra, M. Sakare, A. P. James and D. M. Das, "SpiMAM: CMOS Implementation of Bio-Inspired Spiking Multidirectional Associative Memory Featuring In-Situ Learning," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 72, no. 1, pp. 2-13, Jan. 2025, doi: 10.1109/TCSI.2024.3427387.
S. A. Thomas, S. Kushwaha, R. Sharma and D. M. Das, "Design and Analysis of 3D Integrated Folded Ferro-Capacitive Crossbar Array (FC²A) for Brain-Inspired Computing System," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 14, no. 3, pp. 563-574, Sept. 2024, doi: 10.1109/JETCAS.2024.3432458.
K. Varshney, M. S. Yadav, B. Rawat and D. M. Das, "Analysis and Modeling of Bipolar Resistive Switching in 2-D Graphene Electrode- Based Memristor," in IEEE Transactions on Electron Devices, vol. 70, no. 10, pp. 5454-5461, Oct. 2023, doi: 10.1109/TED.2023.3308525.
M. A. Saeed, M. Kumar, B. Umapathi and D. M. Das, "Optimization of Slew Mitigation Capacitor in Passive Charge Compensation-Based Delta–Sigma Modulator," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 6, pp. 1821-1825, June 2023, doi: 10.1109/TCSII.2023.3234909.
